The present invention relates to divider circuits, and in particular, to circuits and methods that may be used to implement a high frequency division.
Electronic systems often have many different components that include voltage or current signals that have different frequencies. It is often desirable to modify the frequencies of such signals as the signals are used to perform different tasks. One common modification to a signal is frequency division. Frequency division is the process of dividing a signal's frequency by some value (e.g., an integer or fraction). Circuits that perform frequency division are referred to as “Dividers” and are found in a wide variety of electronic applications.
FIG. 1 illustrates a prior art divider circuit. A divider circuit 100 receives an input signal, Vin, and generates an output signal, Vout. The input signal, Vin, may be a square wave, for example, having a period, T1, and a corresponding frequency, F1=1/T1. The output signal, Vout, of divider circuit 100 may have some frequency that is less than the frequency of the input signal, Vin. For example, the output signal, Vout, may have a period, T2, that is twice the value of the input signal period, T1, and thus the output frequency, Fout, has a frequency that is one-half the frequency of the input signal, Vin.
FIG. 2 illustrates a prior art D-Flip Flop divider circuit. The circuit includes two D-flip flops (“DFF”) 201 and 202 connected in series. In this example, each DFF has differential inputs (+in, −in), differential outputs (+out, −out) and differential clock inputs (CK and CK). DFF 201 will load data at its input (i.e., from DFF 202) on the rising edge of CK. Similarly, DFF 202 will load data at its input (i.e., from DFF 201) on the falling edge of CK, which is the rising edge of CK. Thus, each DFF output will transition between logic states once for every period of CK. Consequently, the period of each DFF output is twice the period of the clock, and the output of the divider (+OUT_DIV2, −OUT_DIV2) has one-half the frequency of the clock. DFFs 201 and 202 have, thus, divided the clock frequency by two. Such a circuit is one example of a divide-by-two circuit.
FIG. 3 illustrates another prior art divider circuit 300. Divider 300 shows an implementation of the divider of FIG. 2. Divider 300 includes two differential DFFs. The first DFF includes a first pair of differential transistors M3 and M4 having common sources coupled to ground through transistor M1. The first DFF further includes cross-coupled transistors M5 and M6. M5 and M6 have common sources that are similarly coupled together and to ground through transistor M2. Transistors M5 and M6 form a cross-coupled circuit because the inputs are coupled to the circuit's complementary output. In divider circuit 300, the gate of M5 is coupled to the drain of M6, and the gate of M6 is coupled to the drain of M5. Furthermore, the drain of M5 is coupled to the drain of M4 and the drain of M6 is coupled to the drain of M3. Thus, the cross-coupled devices and the differential pair transistors have common outputs. Differential pair transistors M3/M4 and cross-coupled pair transistors M5/M6 receive bias current from PMOS transistors M7 and M8, which have sources coupled to supply Vdd and gates coupled to a bias voltage Vbias. Transistors M7 and M8 also provide a load impedance to both the differential and cross-coupled pairs.
When transistor M1 receives rising edge transition of the clock input, CK, M1 turns on and activates differential pair M3/M4. Thus, signal values at the gate inputs of M3/M4 (i.e., +in1 and −in1) will drive the outputs of the first DFF (i.e., −out1 and +out1) on the rising edge of CK. During this phase of the clock signal, bias current from transistors M7/M8 is directed through M3, M4 and M1, and the data value at the gate input is stored on the output nodes of the differential pair M3 and M4. When transistor M2 receives a rising edge transition of CK (i.e., the falling edge of CK), M2 turns on while M1 turns off, and cross-coupled pair M5/M6 is activated. During this phase of the clock signal, bias current from transistors M7 and M8 is redirected through M5, M6 and M2, and the data value in the first DFF is maintained by the cross-coupled pair.
The second DFF stage includes transistors M9-M16 connected is the same way as transistors M1-M8 in the first DFF stage. The rising edge of CK triggers the differential input of the second DFF stage (i.e., transistors M11/M12), which causes the data value from the first DFF to drive the outputs of the second DFF. Thus, the signal values at the gate inputs of M11 and M12 (i.e., −in2 and +in2) will drive the outputs of the second DFF (+out2 and −out2) on the rising edge of CK. Referring again to FIG. 2, the two DFFs form a two-stage ring oscillator. The outputs of the second DFF are cross-coupled to the inputs of the first DFF, wherein the positive output of the second DFF (i.e., +out2) is coupled to the negative input of the first DFF (i.e., −in1) and the negative output of the second DFF (i.e., −out2) is coupled to the positive input of the first DFF (i.e., +in1). Thus, the two DFFs operate in opposite states and transition at a frequency of one-half the clock frequency. FIG. 4 illustrates an equivalent implementation wherein resistors and capacitors are used for the load impedance, and bias current is generated using a current source “I” coupled to the sources of transistors M1, M2, M7 and M8.
In high frequency applications, each DFF stage, such as the ones in FIGS. 3-4, may be interpreted as injection-locked oscillators. For example, cross-coupled transistors M5 and M6, together with load transistors M7 and M8 form an oscillator having a center frequency, ωc. When an input signal is provided (e.g., the clock signal in FIG. 3), the divider circuit oscillates at one-half the frequency of the input. However, if the input signal amplitude is too small, or if the frequency of the input signal is outside the lock range of the circuit, then the divider circuit will self-oscillate at a frequency determined by the fundamental frequency (i.e., the center frequency), ωc, of each DFF stage. Thus, in high frequency applications the circuit may operate properly only if the input signal to be divided is within a certain range of frequencies (i.e., the lock range) near the center frequency of the oscillator. To optimize the lock range, it is desirable to have the center frequency, ωc, as close to the center of the lock range as possible. When the center frequency is in the center of the lock range, the input signal may deviate both above and below the center frequency an approximately equal amount and the system will still lock. However, the center frequency of such circuits is subject to deviation from process and temperature variations. These variations can reduce the effective lock range of the circuit, and may cause the circuit to become inoperable.
Thus, there is a need for improved divider circuits, and in particular, for improved circuits and methods that may be used to implement high frequency division with optimized lock range.